1. Field of the Inventive Concept
Embodiments of the present disclosure relate to a non-volatile memory device, and more particularly, to a non-volatile memory device with improved programming speed and data reliability and a method of programming the same.
2. Description of the Related Art
Due to recently increasing demands for portable digital application devices, such as digital cameras, MP3 players, tablet PCs, and smart phones, the market for non-volatile memory devices is rapidly expanding. A memory cell of a flash memory device, which is one of the most popular non-volatile memory devices, generally includes a floating gate, which is disposed on a channel region of a semiconductor substrate and is insulated from the channel region, and a control gate, which is provided on the floating gate and is insulated from the floating gate.
A plurality of memory cells of the flash memory device are generally programmed by using an incremental step pulse program (ISPP) algorithm for applying program pulses having voltage levels, which increase in steps to control gates of respective transistors in a word line consisting of the plurality of memory cells to program the corresponding memory cells. Furthermore, a verification algorithm for checking whether a threshold voltage of a corresponding memory cell reaches a level of a target value Vth is performed after the application of the program pulses.
As integrations and capacities of non-volatile memory devices increase, performance deviation may easily occur between memory cells, and it is difficult to detect defective memory cells by using a program algorithm and a verification algorithm in the related art based on the ISPP algorithm. Such defective memory cells deteriorate a distribution of threshold voltages in programmed memory cells of a corresponding page, thereby causing a chip fail in later read operations. Particularly, as a flash memory is scaled down, the chip fail may occur more frequently due to performance deviation between memory cells. Therefore, it is preferable to detect the defective memory cells time-efficiently during program-verification operations.